A basic integrated MOS transistor circuit is the inverter circuit consisting of an upper MOS transistor connected between a supply voltage and an output terminal and a lower MOS transistor connected between the output terminal and ground. The gate of the upper transistor is connected to a reference voltage, commonly the supply voltage if the transistor is an enhancement type device, and the gate of the lower transistor is connected to an input signal.
In such circuits the width to length ratios of the channel regions of the MOS transistors are principal factors in determining the transconductances of the individual transistors. Conventionally the width to length ratio (W/L)of the upper or load transistor has been set to a relatively low value while the W/L ratio of the lower or driver transistor has been set to a relatively high value to establish voltage gain in the inverter stage.
The low logic level is typically below the threshold voltage of the lower driver transistor such that it is non-conductive and the upper load transistor brings the output to a high voltage. When the input is at a high voltage, the much more conductive driver transistor overpowers the load transistor bringing the output to a low voltage.
As will be shown in more detail later, the gain of an MOS transistor depends also on its channel length. More specifically if an MOS transistor is operating in saturation (i.e. the drain current is essentially independent of drain voltage) and if the length of the channel region between the source and drain areas is relatively short, the transistor tends to operate in a linear fashion, i.e. the drain current is proportional to the gate to source voltage less the transistor threshold voltage. However for devices which have a long channel region, the drain current is proportional to the square of the gate to source voltage less the transistor threshold voltge. For devices having a channel length in between, the drain current is proportional to something between linear and the square of the gate to source voltage less the transistor threshold voltage.
Thus a circuit designer must be aware of the actual length of a MOS channel region which will be used when designing an inverter circuit that has a relatively small voltage signal on the input, particularly when the low input level is above the threshold of the driver transistor. Moreover such a circuit when once designed is not amenable to being scaled larger or smaller to operate in another integrated circuit due to the changes in the nature of the transistor characteristics which are caused by changes in the channel length. This problem is especially acute in special purpose circuits such as an interface circuit designed to receive TTL input signals. A designer would generally want a threshold voltage of about 1.2 volts to make a TTL compatable input inverter stage whereas generally the threshold voltge of the MOS transistors are about half a volt for circuits designed to operate from a 5 volt supply. Thus the input transistor for the TTL signals would require a special threshold adjustment operation in the manufacturing process if a standard inverter is to be used and is to work properly even if the circuit dimensions are changed.
Thus it can be appreciated that an MOS inverter circuit which is not sensitive to variations in channel length and threshold voltages of the MOS transistors is highly desirable.